Application of decision diagrams of incompletely specified of k-valued logic functions in the synthesis of logical circuits

Objectives . The problem of circuit implementation incompletely specified (partial) k-valued logic functions given by tabular representations is considered. stage technologically independent optimization studied to obtain minimized systems completely Boolean from partial logic. According these functions, technological mapping performed at the second synthesis circuits. Methods Using additional definitions Multi-valued Decision Diagrams (MDD) representing logic, and Binary (BDD) proposed. task definition MDD oriented reducing number vertices graph that correspond cofactors Shannon expansion a multi-valued function. Results minimization reduced solving problems coloring undirected graphs incompatibility minimum colors. Encoding values arguments binary codes leads which are also further defined in order minimize their multi-level BDD representations. Conclusion proposed approach makes it possible define fully two stages. At stage, well-known effective methods used redefine functions. As result this two-step approach, obtained. into library logical elements performed, i.e. optimized descriptions function covered with